supleed2/EIE4-FYP
1
0
Fork 0
mirror of https://github.com/supleed2/EIE4-FYP.git synced 2024-12-22 22:25:50 +00:00
Code Issues Packages Projects Releases Wiki Activity

Add comments to sawtooth generator

Browse source
This commit is contained in:
Aadi Desai 2023-05-12 14:00:13 +01:00
parent 012b24adaf
commit 5b66d01ac6
No known key found for this signature in database
1 changed files with 11 additions and 11 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

22
rtl/genSaw.sv
View file

@ -11,29 +11,29 @@ module genSaw
logic [8:0] clk_div;
always_ff @(posedge i_clk48)
if (!i_rst48_n) clk_div <= 0;
else if (clk_div == 9'd500) clk_div <= 0;
else clk_div <= clk_div + 1;
if (!i_rst48_n) clk_div <= 0; // Reset if reset is low
else if (clk_div == 9'd500) clk_div <= 0; // Reset count every 500 cycles
else clk_div <= clk_div + 1; // Increment otherwise
logic clk_48k;
always_ff @(posedge i_clk48)
if (!i_rst48_n) clk_48k <= 0;
else if (clk_div == 9'd500) clk_48k <= ~clk_48k;
if (!i_rst48_n) clk_48k <= 0; // Reset if reset is low
else if (clk_div == 9'd500) clk_48k <= ~clk_48k; // Invert every 500 cycles
logic clk_48k_past;
always_ff @(posedge i_clk48)
clk_48k_past <= clk_48k;
clk_48k_past <= clk_48k; // 1 cycle delayed version of 48kHz clock
assign o_new_pulse = clk_48k && !clk_48k_past;
assign o_new_pulse = clk_48k && !clk_48k_past; // Detect rising edge of 48kHz clock
logic [23:0] saw_step;
assign saw_step = (24'd699 * i_tf) >> 1;
assign saw_step = (24'd699 * i_tf) >> 1; // Sawtooth step calc from input target freq
logic [23:0] waveform;
always_ff @(posedge clk_48k)
if (!i_rst48_n) waveform <= '0;
else if (!i_pause) waveform <= waveform + saw_step;
if (!i_rst48_n) waveform <= '0; // Reset if reset is low
else if (!i_pause) waveform <= waveform + saw_step; // Add saw step if not paused (48kHz)
assign o_lr = {waveform, waveform};
assign o_lr = {waveform, waveform}; // Output same sample to left & right
endmodule