From 48b8e17ff24ae6a4cbd49f354929279718f32010 Mon Sep 17 00:00:00 2001
From: Aadi Desai <21363892+supleed2@users.noreply.github.com>
Date: Wed, 24 May 2023 12:39:11 +0100
Subject: [PATCH] Add ZipCPU article link

---
 readme.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/readme.md b/readme.md
index 88f720d..b489291 100644
--- a/readme.md
+++ b/readme.md
@@ -15,6 +15,7 @@
   - CORDIC Research
     - [Area/Energy Efficient CORDIC Accelerator](https://www.researchgate.net/publication/309549123_Area_and_Energy_efficient_CORDIC_Accelerator_for_Embedded_Processor_Datapaths)
     - [Doulos SNUG Europe 2004 Paper](https://www.doulos.com/knowhow/systemverilog/a-users-experience-with-systemverilog/), [local copy of Verilog](doulos_CORDIC.v)
+    - ZIPcpu: [Using a CORDIC to calculate sines and cosines in an FPGA](https://zipcpu.com/dsp/2017/08/30/cordic.html)
 - [API Reference migen, AsyncFIFO](https://m-labs.hk/migen/manual/reference.html#module-migen.genlib.fifo)
 - [Guide on adding a new core (incomplete)](https://github.com/enjoy-digital/litex/wiki/Add-A-New-Core)
   - [Using LiteEth on ECP5](https://github.com/enjoy-digital/liteeth/issues/66)