diff --git a/doulos_CORDIC.v b/doulos_CORDIC.v deleted file mode 100644 index 0dc8607..0000000 --- a/doulos_CORDIC.v +++ /dev/null @@ -1,391 +0,0 @@ -// CORDIC_par_seq.v Core ALU of a CORDIC rotator, -// word-sequential implementation -// -// Revision information: -// 0.0 07-Jan-2004 Jonathan Bromley -// Initial coding of word-sequential version -// 0.1 08-Jan-2004 Jonathan Bromley -// Still using Verilog-1995 (will migrate to SV3.1 later); -// added angle output and mode-control input, so that it -// can be used to do Cartesian-to-polar conversion as well -// as rotation -// 1.0 15-Jan-2004 Jonathan Bromley -// Migrated everything to signed typedefs (SV3.1) -// and signed arithmetic (see file ../common/defs.v) -// 1.1 25-Jan-2004 Jonathan Bromley -// Improved internal documentation -// __________________________________________________________________________ - - - -// _________________________________________________________ DEPENDENCIES ___ -// -// This module assumes the existence of a typedef T_sdata representing -// signed data. This typedef should be a packed logic or integer. -// The code here will not work correctly if T_sdata, padded with the -// number of additional low-order bits specified by parameter guard_bits, -// is wider than 32 bits - in other words, we require that -// $bits(T_sdata) + guard_bits <= 32 -// __________________________________________________________________________ - - - -//___________________________________________________________ DESCRIPTION ___ -// -// ------- -// PURPOSE -// ------- -// -// This module implements the CORDIC two-dimensional rotator algorithm -// originally proposed by Volder (1959). It can be used to calculate -// trigonometrical functions sin, cos, arctan and others; it can also -// perform polar-to-rectangular and rectangular-to-polar conversion. -// -// -// ---------- -// PARAMETERS -// ---------- -// -// Two parameters, guardBits and stepBits, determine the internal -// behaviour of the CORDIC algorithm. -// -// stepBits is the number of bits in the counter that controls -// iteration of the CORDIC algorithm. In the present implementation -// there will be exactly (2^stepBits) iterations - for example, 16 -// iterations if stepBits=4. As a guideline, (2^stepBits) should be -// at least as large as the number of bits in the data words. -// -// guardBits is the number of additional LSBs that is maintained in -// the internal arithmetic to improve precision. It should normally -// be equal to stepBits, or at least (stepBits-1); otherwise, the -// additional precision gained by additional iterations of the CORDIC -// algorithm will be lost through rounding errors. On the other hand, -// there is little to be gained from making guardBits greater than -// (stepBits+1). -// -// ------------------ -// INPUTS AND OUTPUTS -// ------------------ -// -// There is a single mode control input: -// reduceNotRotate.....sets operating mode of the rotator for the -// next operation - see OPERATION below for details -// -// There are three datapath inputs: -// angleIn.......2s complement signed value, the desired angle of -// rotation -// xIn, yIn......Cartesian coordinates of the point being rotated, -// as 2s complement signed values -// -// There are three datapath outputs: -// angleOut......2s complement signed value, the resulting angle -// after rotation -// xOut, yOut....Cartesian coordinates of the rotated point, -// as 2s complement signed values -// -// There are two operation-control or handshake signals: -// start.........input, should be asserted for one clock at a time when -// valid data are presented to the datapath inputs -// ready.........output, held asserted when datapath outputs carry a -// valid calculation result -// -// The remaining inputs (clock, reset) are the usual positive-edge clock -// and asynchronous power-up reset. -// -// -// --------- -// OPERATION -// --------- -// -// Mode bit "reduceNotRotate" is sampled together with the datapath -// inputs whenever "start" is asserted. -// -// If reduceNotRotate is set (1), angleIn is ignored and the -// CORDIC rotator will rotate the x,y vector so that its y component -// is zero; thus, its x component will reflect the original vector's -// magnitude (scaled by the CORDIC gain) and the angle output will -// be equal to the original vector's argument. This mode provides -// rectangular-to-polar conversion, and calculation of arctangent. -// If the yOut output is significantly different from zero at the end -// of the calculation, it indicates that the argument (angle) of the -// input vector was too far from zero for the CORDIC algorithm to be -// able to reduce it. -// -// If reduceNotRotate is clear (0), the CORDIC rotator will rotate the -// x,y input vector by the angle specified as angleIn (and scale it -// by the CORDIC gain); the output angle will then be close to zero. -// This mode provides polar-to-rectangular conversion, and calculation -// of sine and cosine. If the angleOut output is significantly different -// from zero at the end of the calculation, it indicates that the required -// rotation angle was too large for the CORDIC algorithm to process. -// -// On receipt of a "start" input, the CORDIC processor abandons any -// calculation that may be in progress, clears the "ready" output to zero, -// and starts work on the new input values. When finished, it sets -// "ready" to 1. Whenever "ready" is set, the data outputs -// xOut, yOut, angleOut are valid. These outputs will remain valid, -// and "ready" will remain asserted, until "start" is asserted again at -// some future time. -// -// -// --------------------------- -// MATHEMATICAL CONSIDERATIONS -// --------------------------- -// -// CORDIC gain -// ----------- -// -// It is an inevitable side-effect of the CORDIC algorithm that the -// rotated x,y coordinates are magnified by the CORDIC gain. This -// gain is the product -// -// N-1 -// P (cos(atn(2^(-i)))) -// i=0 -// -// where N is the number of iterations of the CORDIC loop. -// The limit of this product as N tends to infinity is 1.646760258, -// and it approaches this limit quite quickly as N rises - for -// example, its value for N=4 is 1.642484066. For any -// practically useful value of N, it is reasonable to use the limit. -// -// This hardware implementation makes no attempt to account for the -// CORDIC gain, and assumes that this gain factor will be compensated-for -// somewhere else in the system. -// -// Numerical overflow -// ------------------ -// -// The output x,y values from the algorithm can be larger in magnitude than -// the larger of the two (x,y) inputs. For example, if xIn and yIn are -// equal, and the corresponding point is then rotated by pi/4 (45 degrees), -// one of the output coordinates will be zero and the other will be sqrt(2) -// larger than either input. Additionally, the outputs are scaled by the -// CORDIC gain as described above. Consequently, if the largest possible -// input coordinate value is M, then the largest possible output is -// just under 2.33*M. No account is taken of this effect in the hardware; -// input and output values have the same number of bits. It is the user's -// responsibility to ensure that input values do not exceed 1/2.33 times -// the full-scale value - this sets a limit of +/-14106 for 16-bit data. -// -// Scaling of data values -// ---------------------- -// -// Scaling of the Cartesian coordinates is unimportant, except to note -// that the largest magnitude of output results can be as much as -// 2.33 times greater than largest the magnitude of the input, as -// described in "Numerical overflow" above. -// -// Scaling of angles is also quite flexible; any scaling -// can be accommodated, provided the arctan values also have the -// same scaling. Since the CORDIC rotator can rotate its input vector -// by more than one quadrant (pi/2) in either direction, it is -// reasonable and convenient to choose a scaling in which the -// angle is a 2s complement number, with its largest positive value -// (01111...1111) representing just less than +pi and its most -// negative value (10000..0000) representing exactly -pi. -// It is not possible to make effective use of the full range of these -// angles, since the CORDIC algorithm is incapable of rotating a vector -// by more than 1.743 radians (99.8 degrees) in either direction. -// __________________________________________________________________________ - - - - -// This is a synthesisable design and doesn't need a `timescale, -// but we include one here to avoid any dependence on compilation order. -// -`timescale 1ns/1ns - - -//_________________________________________________ module CORDIC_par_seq ___ - -module CORDIC_par_seq -#( parameter - stepBits = 4, // Must be enough to represent 0..angleBits-1 - guardBits = 4 - ) -( - input logic clock, - input logic reset, - - input logic start, - output logic busy, - - input logic reduceNotRotate, - - input T_sdata angleIn, - input T_sdata xIn, - input T_sdata yIn, - - output T_sdata angleOut, - output T_sdata xOut, - output T_sdata yOut -); - - // Copy of reduceNotRotate taken at start time - logic reduceMode; - - localparam sdata_width = $bits(T_sdata); - - typedef logic signed [sdata_width+guardBits-1:0] T_acc; - - // Internal accumulators - T_acc x, y, angle; - - // Internal temporaries - output of combinational blocks - T_acc arctan, scaleX, scaleY; - logic clockwise; - - // Control and sequencing counter - // - logic [stepBits-1:0] step; - - - // ____________________________________________ Combinational stuff ___ - - // Factor-out common functionality: - // - // arctan(2^-n) lookup table - assign arctan = atn(step); - // - // right-shifted coordinates - assign scaleY = y >>> step; - assign scaleX = x >>> step; - // - // convergence direction - assign clockwise = reduceMode ? - // Yes? Then we're trying to reduce y to zero: - // positive y means we should go clockwise. - (y >= 0): - // No? Then we're reducing the angle to zero. - // Negative angle means we should go clockwise. - (angle < 0); - - // Create outputs - // - assign angleOut = angle >>> guardBits; - assign xOut = x >>> guardBits; - assign yOut = y >>> guardBits; - - // ___________________________________________________ Clocked logic ___ - // - always @(posedge clock or posedge reset) - - if (reset) begin - - // dumb initialise - // - angle <= 0; - x <= 0; - y <= 0; - step <= 0; - busy <= 0; - reduceMode <= 0; - - end else if (start) begin - - // initialise, packing working registers with zero LSBs - // - x <= xIn <<< guardBits; - y <= yIn <<< guardBits; - step <= 0; - busy <= 1; - reduceMode <= reduceNotRotate; - if (reduceNotRotate) begin - angle <= 0; - end else begin - angle <= angleIn <<< guardBits; - end - - end else if (busy) begin - - // do one iteration - if (clockwise) begin - - // Angle is negative (or y is positive), - //so we increase the angle and rotate clockwise - angle <= angle + arctan; - x <= x + scaleY; - y <= y - scaleX; - - end else begin - - // Rotate counterclockwise - angle <= angle - arctan; - x <= x - scaleY; - y <= y + scaleX; - - end // if (clockwise)... else... - - if (step == sdata_width-1) begin - // All done at the end of this iteration - busy <= 0; - end // if (step == angleBits) - - step <= step + 1; - - end // if (start) ... else if (active) ... - - - // __________________________________________________ function atn ___ - // - // function atn provides a table of arctan(2^-n) to 32-bit precision, - // and returns the result to the required precision. - // - function T_acc atn; - input [stepBits-1:0] step; - - // internal working register - integer a; - - begin - - // Lookup table. Any unused LSBs will be thrown away - // by synthesis, we hope! - // There is surely no point in having more than 32 iterations? - case (step) - 0: a = 536870912; // atn(1) = pi/4 = 45 degrees = one octant - 1: a = 316933406; - 2: a = 167458907; - 3: a = 85004756; - 4: a = 42667331; - 5: a = 21354465; - 6: a = 10679838; - 7: a = 5340245; - 8: a = 2670163; - 9: a = 1335087; - 10: a = 667544; - 11: a = 333772; - 12: a = 166886; - 13: a = 83443; - 14: a = 41722; - 15: a = 20861; - 16: a = 10430; - 17: a = 5215; - 18: a = 2608; - 19: a = 1304; - 20: a = 652; - 21: a = 326; - 22: a = 163; - 23: a = 81; - 24: a = 41; - 25: a = 20; - 26: a = 10; - 27: a = 5; - 28: a = 3; - 29: a = 1; - 30: a = 1; - 31: a = 0; - default: - a = 0; - endcase // step - - // Rescale result to match internal angle register (typedef T_acc) - atn = a >>> ($bits(integer) - $bits(T_acc)); - - end - endfunction //atn - -endmodule // CORDIC_par_seq -// _______________________________________________________________________ diff --git a/options.sh b/options.sh deleted file mode 100644 index 2abdd1c..0000000 --- a/options.sh +++ /dev/null @@ -1,142 +0,0 @@ -[-h] -[--toolchain {trellis,diamond}] -[--build] -[--load] -[--log-filename LOG_FILENAME] -[--log-level LOG_LEVEL] -[--sys-clk-freq SYS_CLK_FREQ] -[--revision REVISION] -[--device DEVICE] -[--sdram-device SDRAM_DEVICE] -[--with-spi-sdcard] -[--output-dir OUTPUT_DIR] -[--gateware-dir GATEWARE_DIR] -[--software-dir SOFTWARE_DIR] -[--include-dir INCLUDE_DIR] -[--generated-dir GENERATED_DIR] -[--build-backend BUILD_BACKEND] -[--no-compile] -[--no-compile-software] -[--no-compile-gateware] -[--csr-csv CSR_CSV] -[--csr-json CSR_JSON] -[--csr-svd CSR_SVD] -[--memory-x MEMORY_X] -[--doc] -[--bios-lto] -[--bios-console {full,no-history,no-autocomplete,lite,disable}] -[--bus-standard BUS_STANDARD] -[--bus-data-width BUS_DATA_WIDTH] -[--bus-address-width BUS_ADDRESS_WIDTH] -[--bus-timeout BUS_TIMEOUT] -[--bus-bursting] -[--bus-interconnect BUS_INTERCONNECT] -[--cpu-type CPU_TYPE] -[--cpu-variant CPU_VARIANT] -[--cpu-reset-address CPU_RESET_ADDRESS] -[--cpu-cfu CPU_CFU] -[--no-ctrl] -[--integrated-rom-size INTEGRATED_ROM_SIZE] -[--integrated-rom-init INTEGRATED_ROM_INIT] -[--integrated-sram-size INTEGRATED_SRAM_SIZE] -[--integrated-main-ram-size INTEGRATED_MAIN_RAM_SIZE] -[--csr-data-width CSR_DATA_WIDTH] -[--csr-address-width CSR_ADDRESS_WIDTH] -[--csr-paging CSR_PAGING] -[--csr-ordering CSR_ORDERING] -[--ident IDENT] -[--no-ident-version] -[--no-uart] -[--uart-name UART_NAME] -[--uart-baudrate UART_BAUDRATE] -[--uart-fifo-depth UART_FIFO_DEPTH] -[--no-timer] -[--timer-uptime] -[--l2-size L2_SIZE] -[--yosys-nowidelut] -[--yosys-abc9] -[--yosys-flow3] -[--nextpnr-timingstrict] -[--nextpnr-ignoreloops] -[--nextpnr-seed NEXTPNR_SEED] -[--ecppack-bootaddr ECPPACK_BOOTADDR] -[--ecppack-spimode ECPPACK_SPIMODE] -[--ecppack-freq ECPPACK_FREQ] -[--ecppack-compress] - - -# Target options: - --build # Build design. (default: False) - --load # Load bitstream. (default: False) - --sys-clk-freq SYS_CLK_FREQ - # System clock frequency. (default: 48000000.0) - --revision 0.2 - --device 25F - --sdram-device MT41K64M16 - --with-spi-sdcard - # Enable SPI-mode SDCard support. (default: False) - -# Logging options: - --log-filename build.log - --log-level warning # (or debug, info (default), error or critical) - -# Builder options: - --no-compile - # Disable Software and Gateware compilation. (default: False) - --no-compile-software - # Disable Software compilation only. (default: False) - --no-compile-gateware - # Disable Gateware compilation only. (default: False) - --doc # Generate SoC Documentation. (default: False) - -# SoC options: - --bus-standard axi-lite - # Select bus standard: wishbone, axi-lite, axi. (default: wishbone) - --bus-data-width BUS_DATA_WIDTH - # Bus data-width. (default: 32) - --bus-address-width BUS_ADDRESS_WIDTH - # Bus address-width. (default: 32) - --bus-bursting - # Enable burst cycles on the bus if supported. (default: False) - --bus-interconnect BUS_INTERCONNECT - # Select bus interconnect: shared (default) or crossbar. (default: shared) - --cpu-type CPU_TYPE - # Select CPU: None, marocchino, zynq7000, mor1kx, zynqmp, cv32e41p, openc906, cortex_m1, cva6, eos_s3, ibex, - # cortex_m3, blackparrot, femtorv, vexriscv, rocket, picorv32, vexriscv_smp, lm32, firev, serv, naxriscv, cva5, - # microwatt, neorv32, cv32e40p, gowin_emcu, minerva. (default: vexriscv) - --cpu-variant CPU_VARIANT - # CPU variant. (default: None) - --no-ctrl - # Disable Controller. (default: False) - --integrated-rom-size INTEGRATED_ROM_SIZE - # Size/Enable the integrated (BIOS) ROM (Automatically resized to BIOS size when smaller). (default: 131072) - --integrated-rom-init INTEGRATED_ROM_INIT - # Integrated ROM binary initialization file (override the BIOS when specified). (default: None) - --no-uart - # Disable UART. (default: False) - --uart-name UART_NAME - # UART type/name. (default: serial) - --uart-baudrate UART_BAUDRATE - # UART baudrate. (default: 115200) - -# Trellis toolchain options: - --yosys-nowidelut - # Use Yosys's nowidelut mode. (default: False) - --yosys-abc9 - # Use Yosys's abc9 mode. (default: False) - --yosys-flow3 - # Use Yosys's abc9 mode with the flow3 script. (default: False) - --nextpnr-timingstrict - # Use strict Timing mode (Build will fail when Timings are not met). (default: False) - --nextpnr-ignoreloops - # Ignore combinatorial loops in Timing Analysis. (default: False) - --nextpnr-seed NEXTPNR_SEED - # Set Nextpnr's seed. (default: 1) - --ecppack-bootaddr ECPPACK_BOOTADDR - # Set boot address for next image. (default: 0) - --ecppack-spimode ECPPACK_SPIMODE - # Set slave SPI programming mode. (default: None) - --ecppack-freq ECPPACK_FREQ - # Set SPI MCLK frequency. (default: None) - --ecppack-compress - # Use Bitstream compression. (default: False) diff --git a/pcmFifo.py b/pcmFifo.py deleted file mode 100644 index f5c86b3..0000000 --- a/pcmFifo.py +++ /dev/null @@ -1,41 +0,0 @@ -from migen import * - -from litex.soc.interconnect.csr import * -from litex.soc.integration.doc import ModuleDoc - -# CDC FIFO Module for PCM Data --------------------------------------------------------------------- - -class pcmFifo(Module, AutoCSR, ModuleDoc): - """ - DAC Driver Module - - Connect output pins of the DAC - """ - def __init__(self, platform, pads): - self.pads = pads - self.i_clk48 = Signal() - self.i_rst48_n = Signal() - self.i_dvalid = Signal() - self.i_din = Signal(2) - self.o_full = Signal() - self.i_clk36 = Signal() - self.i_rst36_n = Signal() - self.i_rdreq = Signal() - self.o_dout = Signal(2) - self.o_empty = Signal() - - # # # - - self.specials += Instance("pcmfifo", - i_i_clk48=self.i_clk48, - i_i_rst48_n=self.i_rst48_n, - i_i_dvalid=self.i_dvalid, - i_i_din=self.i_din, - o_o_full=self.o_full, - i_i_clk36=self.i_clk36, - i_i_rst36_n=self.i_rst36_n, - i_i_rdreq=self.i_rdreq, - o_o_dout=self.o_dout, - o_o_empty=self.o_empty, - ) - platform.add_source("rtl/pcmfifo.sv") diff --git a/rtl/flip.sv b/rtl/flip.sv deleted file mode 100644 index d9a3347..0000000 --- a/rtl/flip.sv +++ /dev/null @@ -1,29 +0,0 @@ -`default_nettype none - -module flip -( input var i_clk -, output var o_ledr -, output var o_ledg -, output var o_ledb -); - -logic [31:0] counter; -logic [2:0] leds; - -always_ff @(posedge i_clk) - if (counter > 32'd192_000_000) counter <= '0; - else counter <= counter + 1; - -always_comb - if (counter < 24_000_000) {leds} = 3'b000; - else if (counter < 48_000_000) {leds} = 3'b001; - else if (counter < 72_000_000) {leds} = 3'b010; - else if (counter < 96_000_000) {leds} = 3'b011; - else if (counter < 120_000_000) {leds} = 3'b100; - else if (counter < 144_000_000) {leds} = 3'b101; - else if (counter < 168_000_000) {leds} = 3'b110; - else {leds} = 3'b111; - -always_comb {o_ledr, o_ledg, o_ledb} = leds; - -endmodule diff --git a/rtl/pcmfifo.sv b/rtl/pcmfifo.sv deleted file mode 100644 index 63bbb8f..0000000 --- a/rtl/pcmfifo.sv +++ /dev/null @@ -1,109 +0,0 @@ -//////////////////////////////////////////////////////////////////////////////// -// -// The Verilog logic in this module is based on the paper by Clifford E. -// Cummings, of Sunburst Design, Inc, titled: "Simulation and Synthesis -// Techniques for Asynchronous FIFO Design". This paper may be found at -// http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_FIFO1.pdf. -// -// Minor edits to that logic have been made by Gisselquist Technology, LLC. -// Gisselquist Technology, LLC, asserts no copywrite or ownership of these -// minor edits. The edited Verilog file can be found at -// https://github.com/ZipCPU/website/blob/master/examples/afifo.v, which also -// contains many properties (Licensed under GPL, found at -// https://www.gnu.org/licenses/#GPL) for use in Formal Verification. Those -// properties have been removed in this module. -// -//////////////////////////////////////////////////////////////////////////////// - -`default_nettype none - -module pcmfifo -#(parameter int DW = 2 -, parameter int AW = 4 -)(input var i_clk48 -, input var i_rst48_n -, input var i_dvalid -, input var [DW-1:0] i_din -, output var o_full -// ^ 48MHz Domain, v 36MHz Domain -, input var i_clk36 -, input var i_rst36_n -, input var i_rdreq -, output var [DW-1:0] o_dout -, output var o_empty -); - -logic [AW-1:0] w_addr; -logic w_full_next; -logic [AW :0] w_ptr; -logic [AW :0] w_ptr_next; -logic [AW :0] w_ptr_grey; -logic [AW :0] w_ptr_grey_buf1; -logic [AW :0] w_ptr_grey_buf2; -logic [AW :0] w_ptr_grey_next; - -logic [AW-1:0] r_addr; -logic r_empty_next; -logic [AW :0] r_ptr; -logic [AW :0] r_ptr_next; -logic [AW :0] r_ptr_grey; -logic [AW :0] r_ptr_grey_buf1; -logic [AW :0] r_ptr_grey_buf2; -logic [AW :0] r_ptr_grey_next; - -logic [DW-1:0] mem [0:((1 << AW)-1)]; - -// Cross read Grey pointer to Write Domain (48MHz) -always_ff @(posedge i_clk48, negedge i_rst48_n) - if (!i_rst48_n) {r_ptr_grey_buf2, r_ptr_grey_buf1} <= '0; - else {r_ptr_grey_buf2, r_ptr_grey_buf1} <= {r_ptr_grey_buf1, r_ptr_grey}; - -// Calculate next write addr -assign w_addr = w_ptr[AW-1:0]; - -// Calculate next write graycode -assign w_ptr_next = w_ptr + { {(AW){1'b0}}, ((i_dvalid) && (!o_full)) }; -assign w_ptr_grey_next = (w_ptr_next >> 1) ^ w_ptr_next; - -// Register write addr and write graycode -always_ff @(posedge i_clk48, negedge i_rst48_n) - if (!i_rst48_n) {w_ptr, w_ptr_grey} <= 0; - else {w_ptr, w_ptr_grey} <= {w_ptr_next, w_ptr_grey_next}; - -// Update whether fifo is full on next clock -assign w_full_next = (w_ptr_grey_next == {~r_ptr_grey_buf2[AW:AW-1], r_ptr_grey_buf2[AW-2:0] }); -always_ff @(posedge i_clk48, negedge i_rst48_n) - if (!i_rst48_n) o_full <= 1'b0; - else o_full <= w_full_next; - -// Write to FIFO on Write Domain (48MHz) clock -always_ff @(posedge i_clk48) - if ((i_dvalid) && (!o_full)) mem[w_addr] <= i_din; - -// Cross write Grey pointer to Read Domain (36MHz) -always_ff @(posedge i_clk36, negedge i_rst36_n) - if (!i_rst36_n) {w_ptr_grey_buf2, w_ptr_grey_buf1} <= 0; - else {w_ptr_grey_buf2, w_ptr_grey_buf1} <= {w_ptr_grey_buf1, w_ptr_grey}; - -// Calculate next read address -assign r_addr = r_ptr[AW-1:0]; - -// Calculate next read graycode -assign r_ptr_next = r_ptr + { {(AW){1'b0}}, ((i_rdreq) && (!o_empty)) }; -assign r_ptr_grey_next = (r_ptr_next >> 1) ^ r_ptr_next; - -// Register read addr and read graycode -always_ff @(posedge i_clk36, negedge i_rst36_n) - if (!i_rst36_n) {r_ptr, r_ptr_grey} <= 0; - else {r_ptr, r_ptr_grey} <= {r_ptr_next, r_ptr_grey_next}; - -// Update whether fifo is empty on next clock -assign r_empty_next = (r_ptr_grey_next == w_ptr_grey_buf2); -always_ff @(posedge i_clk36, negedge i_rst36_n) - if (!i_rst36_n) o_empty <= 1'b1; - else o_empty <= r_empty_next; - -// Output read data combinatorially -assign o_dout = mem[r_addr]; - -endmodule \ No newline at end of file diff --git a/testLED.py b/testLED.py deleted file mode 100644 index 2e80a82..0000000 --- a/testLED.py +++ /dev/null @@ -1,23 +0,0 @@ -from migen import * -from migen.genlib.misc import WaitTimer - -from litex.soc.interconnect.csr import * - -# Test LED Module ---------------------------------------------------------------------------------- - -class TestLed(Module, AutoCSR): - def __init__(self, platform, pads): - self.pads = pads - leds = Signal(3) - - # # # - - self.comb += pads.eq(leds) - self.specials += Instance("flip", - i_i_clk = ClockSignal("dac"), - o_o_ledr = leds[0], - o_o_ledg = leds[1], - o_o_ledb = leds[2] - ) - platform.add_source("rtl/flip.sv") -