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Update testSaw to match updated genSaw / dacDriver

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Aadi Desai 2023-05-16 22:13:24 +01:00
parent 06fc184cc5
commit 3190265343
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1 changed files with 25 additions and 29 deletions
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36
testSaw.py
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@ -1,6 +1,8 @@
from migen import * from migen import *
from litex.soc.interconnect.csr import * from litex.soc.interconnect.csr import *
from litex.soc.interconnect.stream import AsyncFIFO
from migen.genlib.fifo import AsyncFIFO as MigenAsyncFIFO
from litex.soc.integration.doc import ModuleDoc from litex.soc.integration.doc import ModuleDoc
# Test RGB Module ---------------------------------------------------------------------------------- # Test RGB Module ----------------------------------------------------------------------------------
@ -13,7 +15,6 @@ class TestSaw(Module, AutoCSR, ModuleDoc):
""" """
def __init__(self, platform, pads): def __init__(self, platform, pads):
platform.add_source("rtl/genSaw.sv") platform.add_source("rtl/genSaw.sv")
platform.add_source("rtl/pcmfifo.sv")
platform.add_source("rtl/dacDriver.sv") platform.add_source("rtl/dacDriver.sv")
self.pads = pads self.pads = pads
@ -21,12 +22,12 @@ class TestSaw(Module, AutoCSR, ModuleDoc):
# 48MHz Domain Signals # 48MHz Domain Signals
self.backpressure_48 = Signal() self.backpressure_48 = Signal()
self.leftrightaudio_48 = Signal(48) self.sample_48 = Signal(16)
self.audioready_48 = Signal() self.audioready_48 = Signal()
# 36.864MHz Domain Signals # 36.864MHz Domain Signals
self.readrequest_36 = Signal() self.readrequest_36 = Signal()
self.leftrightaudio_36 = Signal(48) self.sample_36 = Signal(16)
self.fifoempty_36 = Signal() self.fifoempty_36 = Signal()
self.dac_lrck = Signal() self.dac_lrck = Signal()
self.dac_bck = Signal() self.dac_bck = Signal()
@ -38,30 +39,25 @@ class TestSaw(Module, AutoCSR, ModuleDoc):
i_i_clk48 = ClockSignal(), i_i_clk48 = ClockSignal(),
i_i_rst48_n = ~ResetSignal(), i_i_rst48_n = ~ResetSignal(),
i_i_pause = self.backpressure_48, i_i_pause = self.backpressure_48,
i_i_tf = self.targ.storage, i_i_targetf = self.targ.storage,
o_o_lr = self.leftrightaudio_48, o_o_sample = self.sample_48,
o_o_new_pulse = self.audioready_48, o_o_pulse = self.audioready_48,
) )
self.specials += Instance("pcmfifo", sample_fifo = ClockDomainsRenamer({"write": "sys", "read": "dac"})(MigenAsyncFIFO(48, 4))
i_i_clk48 = ClockSignal(), self.comb += self.backpressure_48.eq(~sample_fifo.writable)
i_i_rst48_n = ~ResetSignal(), self.comb += sample_fifo.we.eq(self.audioready_48)
i_i_dvalid = self.audioready_48, self.comb += sample_fifo.din.eq(self.sample_48)
i_i_din = self.leftrightaudio_48, self.comb += self.fifoempty_36.eq(~sample_fifo.readable)
o_o_full = self.backpressure_48, self.comb += sample_fifo.re.eq(self.readrequest_36)
# ^ 48MHz Domain, v 36MHz Domain self.comb += self.sample_36.eq(sample_fifo.dout)
i_i_clk36 = ClockSignal("dac"), self.submodules += sample_fifo
i_i_rst36_n = ResetSignal("dac"),
i_i_rdreq = self.readrequest_36,
o_o_dout = self.leftrightaudio_36,
o_o_empty = self.fifoempty_36,
)
self.specials += Instance("dacDriver", self.specials += Instance("dacDriver",
i_i_clk36 = ClockSignal("dac"), i_i_clk36 = ClockSignal("dac"),
i_i_rst36_n = ~ResetSignal("dac"), i_i_rst36_n = ~ResetSignal("dac"),
i_i_wait = self.fifoempty_36, i_i_wait = self.fifoempty_36,
i_i_lraudio = self.leftrightaudio_36, i_i_sample = self.sample_36,
o_o_rdreq = self.readrequest_36, o_o_rdreq = self.readrequest_36,
o_o_lrck = self.dac_lrck, o_o_lrck = self.dac_lrck,
o_o_bck = self.dac_bck, o_o_bck = self.dac_bck,