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Make soft wave end signed
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@ -60,9 +60,9 @@ always_ff @(posedge i_clk48) phase_step[ps_clk] <= {1'b0, int_phase_step[23:9]};
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logic [15:0] phase [0:63];
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for (genvar i = 0; i < 64; i++) begin: l_gen_phase
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always_ff @(posedge clk_48k) // Generate new phase sample on rising edge of 48kHz clock
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if (!i_rst48_n) phase[i] <= 16'd0; // Reset saw
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else if (phase_step[i] == 16'd0) phase[i] <= phase[i] >> 1; // Divide by 2 if phase_step is 0
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else if (!i_pause) phase[i] <= phase[i] + phase_step[i]; // Add phase_step if not paused (48kHz)
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if (!i_rst48_n) phase[i] <= 16'd0; // Reset saw
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else if (phase_step[i] == 16'd0) phase[i] <= {phase[i][15], phase[i][15:1]};// Divide by 2 if phase_step is 0
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else if (!i_pause) phase[i] <= phase[i] + phase_step[i]; // Add phase_step if not paused (48kHz)
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end
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// Per Oscillator Sample Generation ################################################################
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