From 0faa2a92cc77dad14bf76261ae7967de286a384b Mon Sep 17 00:00:00 2001
From: Aadi Desai <21363892+supleed2@users.noreply.github.com>
Date: Fri, 19 Jan 2024 21:57:58 +0000
Subject: [PATCH] Update readme

---
 readme.md | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/readme.md b/readme.md
index 1a265f9..78df3d5 100644
--- a/readme.md
+++ b/readme.md
@@ -7,3 +7,5 @@ StackSynth is an educational synthesizer platform based on the STM32L432, used i
 The goal of this project was to create the SystemVerilog modules and code for an FPGA-based extension module for StackSynth, to increase the audio ability and performance of the synthesizer while providing future Embedded Systems students an opportunity to develop code for an integrated [VexRiscV](https://github.com/SpinalHDL/VexRiscv) RISC-V System-on-Chip.
 
 Notes taken during this project primarily consist of links for useful reading and reference materials, and is available in [this document](./notes/readme.md).
+
+A second branch [`report`](https://github.com/supleed2/EIE4-FYP/tree/report) also contains presentation materials and draft report notes.