mirror of
https://github.com/supleed2/EIE4-FYP.git
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75 lines
2.6 KiB
Python
75 lines
2.6 KiB
Python
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from migen import *
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from litex.soc.interconnect.csr import *
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from litex.soc.integration.doc import ModuleDoc
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# Test RGB Module ----------------------------------------------------------------------------------
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class TestSaw(Module, AutoCSR, ModuleDoc):
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"""
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Sawtooth Wave Test Module
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Set the expected frequency sawtooth wave to be output via the headphone port.
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"""
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def __init__(self, platform, pads):
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platform.add_source("rtl/genSaw.sv")
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platform.add_source("rtl/pcmfifo.sv")
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platform.add_source("rtl/dacDriver.sv")
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self.pads = pads
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self.targ = CSRStorage(size = 24, description="Target Frequency of the Sawtooth Wave")
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# 48MHz Domain Signals
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self.backpressure_48 = Signal()
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self.leftrightaudio_48 = Signal(48)
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self.audioready_48 = Signal()
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# 36.864MHz Domain Signals
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self.readrequest_36 = Signal()
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self.leftrightaudio_36 = Signal(48)
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self.fifoempty_36 = Signal()
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self.dac_lrck = Signal()
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self.dac_bck = Signal()
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self.dac_data = Signal()
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# # #
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self.specials += Instance("genSaw",
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i_i_clk48 = ClockSignal(),
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i_i_rst48_n = ResetSignal(),
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i_i_pause = self.backpressure_48,
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i_i_tf = self.targ.storage,
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o_o_lr = self.leftrightaudio_48,
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o_o_new_pulse = self.audioready_48,
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)
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self.specials += Instance("pcmfifo",
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i_i_clk48 = ClockSignal(),
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i_i_rst48_n = ResetSignal(),
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i_i_dvalid = self.audioready_48,
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i_i_din = self.leftrightaudio_48,
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o_o_full = self.backpressure_48,
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# ^ 48MHz Domain, v 36MHz Domain
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i_i_clk36 = ClockSignal("dac"),
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i_i_rst36_n = ResetSignal("dac"),
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i_i_rdreq = self.readrequest_36,
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o_o_dout = self.leftrightaudio_36,
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o_o_empty = self.fifoempty_36,
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)
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self.specials += Instance("dacDriver",
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i_i_clk36 = ClockSignal("dac"),
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i_i_rst36_n = ResetSignal("dac"),
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i_i_wait = self.fifoempty_36,
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i_i_lraudio = self.leftrightaudio_36,
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o_o_rdreq = self.readrequest_36,
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o_o_lrck = self.dac_lrck,
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o_o_bck = self.dac_bck,
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o_o_data = self.dac_data,
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)
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self.comb += self.pads.sck.eq(ClockSignal("dac"))
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self.comb += self.pads.bck.eq(self.dac_bck)
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self.comb += self.pads.lrck.eq(self.dac_lrck)
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self.comb += self.pads.data.eq(self.dac_data)
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